1. Field of the Invention
The present invention generally relates to a semiconductor structure, and a method for forming a landing pad with a maximized area. Specifically speaking, the present invention relates to a method for forming a landing pad with a maximized area to obtain a semiconductor structure with a maximized area serving as landing pads. In such a way, a reticle process maybe omitted and the area for landing pads is maximized, which is favorable for a process window as larger as possible.
2. Description of the Prior Art
A semiconductor element is a basic structure for most of the electronic components. In a semiconductor element structure, there are usually functional components, such as a source, a drain and a gate. Further in the core region and in the peripheral region, there are also semiconductor elements of different functions. Still, in order to be able to accommodate semiconductor elements as many as possible, the use of a buried gate structure is a prevailing trend.
However, on one hand, the buried gate structure which is deeply buried in the interlayer dielectric layer and in the substrate must be externally electrically connected by an upward plug. However, since the buried gate structures which are deeply buried in the interlayer dielectric layer and in the substrate are so densely arranged, plus the intrinsic limitations of the lithographic resolution (exposure resolution), the landing pad area which serves as the contact plugs is getting less and less adequate and the result takes its toll on the process window of follow procedures seriously. On the other hand, because the functions of the semiconductor elements are different in the core region and in the peripheral region, different steps are required to respectively construct the etching holes which are needed by landing pads of different functions so the overall process becomes more complicated.
As a result, it is still needed to develop a novel semiconductor structure as well as a corresponding method of forming the same, to obtain a semiconductor structure with a maximized area for landing pads.